Lab. News

Japanese

Three presentations related to our lab are presented at ISSCC'07.

# M.Takamiya, T.Sekitani, Y.Miyamoto, Y.Noguchi, H.Kawaguchi, T.Someya and T.Sakurai, "Design Solutions for a Multi-Object Wireless Power Transmission Sheet Based on Plastic Switches," Paper#20.4, ISSCC'07, Feb. 2007.

# N.Miura, H.Ishikuro, T.Sakurai, T.Kuroda, "A 0.14pJ/b Inductive-Coupling Inter-Chip Data Transceiver with Digitally-Controlled Precise Pulse Shaping," Paper#20.2, ISSCC, Feb. 2007.

# T.Sakurai, "Organic-transistor circuit design (tutorial)," invited, T8, ISSCC'07, Feb. 2007.

(Nov. 28th, 2006)

Two papers from our lab are accepted for presentation for the forthcoming Custom Integrated Circuits Conference 2006 held in San Jose.

# Atit Tamtrakarn, Hiroki Ishikuro, Koichi Ishida and Takayasu Sakurai, "Compact outside-rail circuit structure by single-cascode two-transistor topology," CICC 2006, 17.4, Sep.2006.

# Kohei Onizuka, Hiroshi Kawaguchi, Makoto Takamiya, Tadahiro Kuroda and Takayasu Sakurai, "Chip-to-Chip Inductive Wireless Power Transmission System for SiP Applications," CICC 2006, 15.1, Sep.2006.

(Jun. 28th, 2006)

The following two papers are on the list of Top Cited Articles in the Journal of Solid-State Circuits. Related site

# T.Sakurai, A.R.Newton, "Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas," IEEE JSSC, Vol.SC-25, No.2, pp. 584-94 Apr. 1990.

# T.Sakurai, "Approximation of wiring delay in MOSFET LSI," IEEE JSSC, Vol.SC-18, No.4, pp. 418-426 Aug. 1983.

(Apr. 14th, 2006)

Two papers from our lab are accepted for presentation for the forthcoming Symposium on VLSI Circuits 2006 held in Hawaii.

# Kenichi Inagaki, Danardono Dwi Antono, Makoto Takamiya, Shigetaka Kumashiro, and Takayasu Sakurai, "A 1-ps resolution on-chip sampling oscilloscope with 64:1 tunable sampling range based on ramp waveform division scheme," Symp. on VLSI circ. 2006, 8.1, June 2006.

# Atit Tamtrakarn, Hiroki Ishikuro, Koichi Ishida, Makoto Takamiya, Takayasu Sakurai, "A 1-V 299µW Flashing UWB Transceiver Based on Double Thresholding Scheme," Symp. on VLSI circ. 2006, 23.2, June 2006.

(Mar. 9th, 2006)

Two papers related to our lab were presented at ISSCC'06.

# M. Takamiya, T. Sekitani, Y. Kato, H. Kawaguchi, T. Someya, T. Sakurai, "An Organic FET SRAM for Braille Sheet Display with Back Gate to Increase Static Noise Margin," ISSCC'06, Paper#15.4, Feb. 2006.

# N. Miura, D. Mizoguchi, M. Inoue, K. Niitsu, Y. Nakagawa, M. Tago, M. Fukaishi, T. Sakurai, T. Kuroda, "A 1Tb/s 3W Inductive-Coupling Transceiver for Inter-Chip Clock and Data Link," ISSCC'06, Paper#23.4, Feb. 2006.

(Mar. 13th, 2006)

Prof. Sakurai was awarded the Patent of the Year by Precision and Intelligence Lab. Related site

Related documents:
Comments from committee(.doc)
Patent press release(.pdf)
(Nov. 11th, 2005)

Three papers from our lab are accepted for presentation for the forthcoming Asian Solid-State Circuits Conference 2005 held in Hsinchu, Taiwan.

# K.Ishida, A.Tamtrakarn, H.Ishikuro, and T.Sakurai, "An Outside-Rail Opamp Design Targeting for Future Scaled Transistors," A-SSCC'05, Paper#2.4, Nov. 2005.

# C.Q.Tran, H.Kawaguchi, and T.Sakurai, "95% Leakage-Reduced FPGA using Zigzag Power-gating Dual-VTH/VDD and Micro-VDD-Hopping," A-SSCC'05, Paper#6.2, Nov. 2005.

# K.Onizuka and T.Sakurai, "VDD-Hopping Accelerator for On-Chip Power Supplies Achieving Nano-Second Order Transient Time," A-SSCC'05, Paper#6.1, Nov. 2005.

(Aug. 19th, 2005)

Three papers from our lab are accepted for presentation for the forthcoming Symposium on VLSI Circuits 2005 held in Kyoto.

# K.W.Choi, Y.Xu, and T.Sakurai "Optimal Zigzag (OZ): An Effective Yet Feasible Power-Gating Scheme Achieving Two Orders of Magnitude Lower Standby Leakage," Proc. of Symposium on VLSI Circuits, accepted for presentation, Jun. 2005.

# F.R.Saliba, H.Kawaguchi, T.Sakurai, "Experimental Verification of Row-by-Row Variable VDD Scheme Reducing 95% Active Leakage Power of SRAM's," Proc. of Symposium on VLSI Circuits, accepted for presentation, Jun. 2005.

# K.Ishida, K.Kanda, A.Tamtrakarn1, H.Kawaguchi, and T.Sakurai, "Managing Leakage in Charge-Based Analog Circuits with Low-VTH Transistors by Analog T- Switch (AT-Switch) and Super Cut-off CMOS," Proc. of Symposium on VLSI Circuits, accepted for presentation, Jun. 2005.

(Mar. 4th, 2005)

A revolutionary sheet-type scanner based on organic transistors were presented at the IEDM and covered by the press. Circuit innovation associated with the scanner will be presented at the forthcoming ISSCC'05 next February at San Francisco.
http://www.nikkei.co.jp/news/sangyo/20041210AT1D1003S10122004.html
http://www.business-i.jp/news/electric/art-20041210204227-KIQWCWRWOG.nwc
http://www.mainichi-msn.co.jp/shakai/photojournal/news/20041211k0000m0400360 00c.html
(Dec. 21st, 2004)

The papers from all the Ph.D graduates from our lab. got accepted for the ISSCC'05. Other papers related to our lab were also accepted for presentation at ISSCC'05.
(Oct. 22nd, 2004)

Following paper was cited many times and selected as a paper of fame for IEEE Journal of Solid-State Circuits.
T.Sakurai and A.R.Newton, "Alpha-Power Law MOSFET Model and Its Applications to CMOS Inverter Delay and Other Formulas"
(Oct. 1st, 2004)

K.Tokunaga received the best presentation award in the 2004 STARC symposium for "Investigation of low power library using dual-VTH, dual-VDD, and dual-W".
(Sep. 9th, 2004)

IEEE Distinguished Lecturer Program "Perspectives of Low Power Electronics" will be held in Taiwan on Mar. 15-16, 2004. Details
(Feb. 10th, 2004)

Electronic artificial skin for robots is developed based on organictransistors. Click here for details (available only in Japanese)

Related Papers

T. Someya and T. Sakurai, "Integration of Organic Field-Effect Transistors and Rubbery Pressure Sensors for Artificial Skin Applications" (IEDM 2003)

T. Someya, H. Kawaguchi, and T. Sakurai, "Cut-and-Paste Organic FET Customized ICs for Application to Artificial Skin" (ISSCC 2004)
(Nov. 21st, 2003)

Our lab received IP Awards three years in a row from LSI IP Design Award Committees. Details in Japanese
(Jun. 10th, 2003)

We received two desktop PC's as gifts from Intel Corporation for research on "Low-leakage / leakage-tolerant CMOS memory design."
(Sep. 8th, 2003)

We are designated as a frequent contributor to the ISSCC for these 50 years.
(Mar. 3rd, 2003)

Prof. Sakurai became an IEEE CAS Distinguished Lecturer.
(Mar. 3rd, 2003)

Prof. Sakurai received the "ISSCC 2002 Outstanding Evening Panel Award" for "Low-Voltage Design or the End of MOSFET Scaling?" as a moderator for the panel.
This award will be officially announced and presented at the Plenary Session of ISSCC 2003 on the morning of Monday, February 10, 2003.
(Jan. 6th, 2003)

Prof. Takayasu Sakurai received the IEEE fellow grade with the following citation:
-- for contributions to the modeling and design of high speed VLSI circuits. IEEE Class of 2003 Fellows
(Nov. 20th, 2002)

From our lab., the following 4 papers, including 1 plenary, are accepted by the forthcoming IEEE International Solid-State Circuits Conference (ISSCC) 2003.

H. Kawaguchi, K. Kanda, K. Nose, S. Hattori, D. D. Antono, D. Yamada, T. Miyazaki, K. Inagaki, T. Hiramoto, and T. Sakurai, "A 0.5-V, 400-MHz, VDD-Hopping Processor with Zero-VTH FD-SOI Technology"

K. Kanda, D. D. Antono, K. Ishida, H. Kawaguchi, T. Kuroda, and T. Sakurai, "1.27-Gbps/pin, 3mW/pin Wireless Superconnect (WSC) Interface Scheme"

Kyeong-Sik Min and Takayasu Sakurai, "Zigzag Super Cut-off CMOS (ZSCCMOS) Block Activation with Self-Adaptive Voltage Level Controller: An Alternative to Clock-Gating Scheme in Leakage Dominant Era"

Takayasu Sakurai, "Perspectives on Power-Aware Electronics (Plenary Talk)"
(Oct. 18th, 2002)

Our lab received IP Awards two years in a row from LSI IP Design Award Committees. Details in Japanese
(May, 23rd, 2002)

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